Method of fabricating integrated circuit with improved yield rate
US5444000A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1994 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Mar 3, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating semiconductor integrated circuits with an improved yield rate is realized, which requires no special circuits for selecting normal circuit blocks. Removable temporary wires are connected to circuit blocks, which are thus tested. After removing the temporary wires, a plurality of normally-operating circuit blocks are interconnected by new main wires. The need of a special selecting circuit for replacing defective circuit blocks with normal circuit blocks is eliminated without increasing the delay time due to redundancy. The freedom of the main wiring formed after removal of the temporary wires is so high that the functional freedom of the system constructed is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.