Tie-up and tie-down circuits with a primary input for testability improvement of logic networks
US5444391A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1994 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Feb 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor product logic chip (20) including a logic network (27-1) to be fed by a tie-up/tie down circuit (21-1). A tie-up/tie-down circuit is comprised of a non-inverting buffer book (22-1) whose input terminal (23-1) is controlled from the outside by a connection (25) to a primary input terminal (24) of the said chip. Its output terminal (26-1) is connected to said logic network. The primary input terminal is connected to a voltage supply means (29) capable of supplying a constant supply voltage VDD/GND in the SYSTEM mode and a supply voltage varying between VDD and GND, during the TEST mode. When the chip operates in the SYSTEM mode, the supply voltage means is the VDD/GND power supply, so that the primary input terminal is directly tied to the VDD/GND power supply. As a result, the tie-up/tie-down circuit generates a steady logic level "1"/"0" on its output terminal. Unlike, in the TEST mode, the voltage supply means consists of the tester generator so that the tie-up/tie-down circuit follows the tester stimuli sequence. As a result, the output terminal of the tie-up/tie-down circuit switches between the "1" and "0" logic levels depending on the tester stimuli. This allow…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.