PLD with selective inputs from local and global conductors
US5444394A · kind A · utility
141Cited by
10References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1993 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Jul 8, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array blocks include CMOS look up table based logic modules that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.