Level shifting circuit
US5444396A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1994 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Sep 21, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit for converting a lower logic level into a higher logic level is arranged to prevent a large through current from flowing when the level of an input signal varies. A latch circuit for latching an input binary signal comprises first and second transistors to which there are connected in series third and fourth transistors, respectively, for blocking a current during the level shifting period. Fifth and sixth transistors having a small current capacity are connected parallel to the set of first and third transistors and the set of second and fourth transistors, respectively, to quickly respond to a level change. The fifth and sixth transistors may be dispensed with.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.