Mixer circuit
US5444399A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1993 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Aug 20, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a mixer circuit, a first gate 25a of a dual gate MESFET 1 having pulse doped structure is connected through a filter 4 to an LO signal input terminal 5, and a second gate 25b is connected through a matching circuit 6 to an RF signal input terminal 7. The drain 27 of the FET 1 is connected through a low-pass filter 10 to an output terminal 11. The gate bias point of the first gate 25a is set in the vicinity of the pinch-off point of the mutual conductance, and the gate bias point of the second gate 25b is set in the area where the mutual conductance is unvaried with increase of the gate voltage. With this arrangement, the mixer circuit can be so designed that the isolation characteristic of the RF signal and the LO signal is excellent, and a stable operational characteristic can be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.