Optimized electronic operation of digital micromirror devices
US5444566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1994 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Mar 7, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S359/904
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for controlling a digital micromirror device 40 resulting in decreased mechanical stress, longer device lifetimes, decreased incidence of spontaneous bit reset, and increased pulse-width modulation accuracy. To reduce the device stress, the bias voltage 142 applied to the mirror 50 may be reduced after the mirror 50 has been latched. To prevent premature mirror changes, the address electrode bias voltage 140 may be reduced after the mirror is driven to the desired position. To ensure that the mirror 50 returns to the neutral position during reset, the mirror bias voltage 142 may be raised from ground potential to approximately halfway between the two addressing voltages during the reset period 152. To reduce the effects of hinge memory and to ensure that the mirror 50 rotates toward the proper address electrode, the mirror bias voltage 142 may be gradually increased to allow the mirror 50 time to rotate towards the proper address electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.