Power on reset signal circuit with clock inhibit and delayed reset
US5446403A · kind A · utility
24Cited by
7References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 4, 1994 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Feb 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control circuit inhibits the CLOCK input to the CPU during power-up to prevent newer submicron CPUs from locking up during a power-up condition. The control circuit also provides a delayed control signal representing that the power supply has stabilized. This delayed control signal is used to consistently control the RESET signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.