Method and apparatus for reducing jitter and improving testability of an oscillator
US5446420A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1993 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Aug 25, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oscillator such as a pulled-crystal oscillator (50) provides low clock jitter by converting a sinusoidal voltage on a crystal's (51) terminals into a digital square wave with a comparator (56). The oscillating frequency of the crystal (51) is pulled by selectively switching in extra capacitance through capacitor digital-to-analog converters (CDACs) (57, 58). The oscillator (50) has built-in testability which allows individual capacitors in the CDACs (57, 58) to be quickly tested for opens. A scan path is connected to the inputs of the CDACs (57, 58) for selecting individual capacitors. A first input terminal of the comparator (56) is precharged before a capacitor under test (171) is connected. A comparison voltage is provided to the second input terminal. The capacitor under test (171) is determined to be functional if, after being connected to the first input terminal of the comparator (56), it discharges the first input terminal to a voltage below the comparison voltage, causing the comparator (56) to switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.