Auto-calibrated current-mode digital-to-analog converter and method therefor
US5446455A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 1993 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Dec 2, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current-mode DAC (20) includes two sub-DACs (22, 36), and a calibrated attenuator (48). One sub-DAC (22) receives least-significant-bits (LSB) of a K-bit digital input signal, and the second sub-DAC (36) receives most-significant-bits (MSB) of the K-bit digital input signal. An output of the sub-DAC (22) is attenuated by an attenuator (50), and the attenuated signal is summed with an output of the second sub-DAC (36) to form an analog output signal. A 4-phase gain adjust sample and hold circuit (49) is used to calibrate the attenuator (50). The 4-phase gain adjust sample and hold circuit (49) samples the current from the attenuator (50), and removes device mismatch effects in the attenuator (50) which cause linearity errors in the current-mode DAC (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.