Split multiply operation
US5446651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1993 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Nov 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplier (220) selectively multiplies either a pair of 2N bit digital numbers or two pair of N bit digital numbers. The multiplier (220) includes a first input encoding circuit (350), a second input encoding circuit (352), a number of partial product generators (353, 354, 356, 363, 364, 366) and a set of adders (355, 357, 365, 367, 368, 369). The first input encoder circuit (350) generates partial product control signals from a first data word holding either a first 2N bit number or a first pair of N bit numbers. The second input encoding circuit (352) generates partial product input signals to the partial product generators (353, 354, 356, 363, 364, 366) from a second data word holding either a second 2N bit number or a second pair of N bit numbers. A first set of adders (355, 357) forms a weighted first sum of the first set of partial products signals. A second set of adders (365, 367) forms a weighted second sum of said second set of partial product signals. A third adder ( 368) forms a weighted sum of the first and second sums. The multiplexer (369) forms an output from the third adder in the 2N by 2N multiplication mode and forms an output having least significant bits cor…
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