Peripheral memory interface controller as a cache for a large data processing system
US5446844A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1991 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Aug 5, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface controller coupled between the main memory system and the I/O system of a large data processing system which controller is able to receive memory access requests from a number of different peripheral devices. The memory interface controller is provided with a data array for holding a number of data words fetched from memory which data array in turn is addressed by the output of an address array. The address array is an associative memory that can associate a given main memory address, of data in the data array, with a data array address containing data stored in main memory at that main memory address so that actual main memory access need not be required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.