Method of reducing noise signals caused by fluctuations in power requirements of digital signal processor having recurring wait routines
US5446852A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1994 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Aug 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method utilizing a predetermined set of instructions in a wait routine reduces spurious signals caused by the power consumption of processors, particularly digital signal processors, which is dependent on the instruction code being executed. These spurious signals occur, for example, in processors performing cyclically recurring program routines which are initiated by interrupts where, during the run time of the routines, a first mean power consumption results, and where the run time of the program routines is shorter than the time between two successive interrupts. The cyclic changes in power consumption caused by this mode of operation of the digital signal processor are avoided by performing a wait routine between successive program routines which includes instructions selected to cause a mean power consumption of the processor during the wait routine to correspond to that during the program routines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.