Microprocessor PLL clock circuit with selectable delayed feedback
US5446867A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1992 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | May 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for use in high performance microprocessor systems which eliminates skew between a clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core. The circuit includes a phase locked loop (PLL), a delay line and a clock driver. The PLL locks and deskews the external clock edge to that of the internal clock to thereby provide an overall reduction of the setup and hold time window to satisfy the tight I/O timings required by high performance microprocessor systems. By incorporating the same PLL in all the closely coupled components of the microprocessor core, similar temperature and power supply tracking of such components is achieved. The PLL is a charge-pump based circuit of the type known in the art incorporating a phase detector, charge pump, loop filter and voltage controlled oscillator (VCO). However, the inclusion of the delay line in the feedback path of the PLL provides advantages not available from PLLs without such a delay line. A programmable tap is provided in the delay line which allows the I/O circuitry of the microprocessor to work with either CMOS or TTL input specifications. Specifically, compens…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.