Memory checker
US5446873A · kind A · utility
5Cited by
4References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1993 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Oct 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new memory checker comprised of a parity checker (51), a bit storage (52), and a parity generator (53), and installed in the memory module (20) of a computer system (10) for checking data error, wherein the parity checker (51) receives the data bus and input parity signal from the computer system (10) to check out error from the data been fetched from the memory module (20) and then to provide an interrupt signal (43) to the computer system (10) upon the checking of an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.