Self-aligned process for capping copper lines
US5447599A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 9, 1994 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Jun 9, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24917
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C., and then usually at temperatures ranging from between 550.degree. C. to 650.degree. C. for approximately five minutes. The copper lines are thereby capped with a layer of TiN(O), since oxygen is incorporate…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.