Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish
US5447874A · kind A · utility
Inventors
Key dates
| Filing date | Jul 29, 1994 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Jul 29, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device gate is provided that reduces gate length variability while maintaining self-alignment and eliminating etch damage and substrate contamination. A gate opening (18) is formed in an oxide layer (16) using a anisotropic etch. The anisotropic etch creates a reverse gate metal image that has low gate length variability. Dual metal gate (26) is then deposited. The excess gate metal is then removed and the top surface (31) of the gate (30) planarized using a chemical mechanical polish. The remaining oxide (16) is then removed, leaving a precise gate (30). The use of a nitride barrier (12) and of an etchstop layer (14) of aluminum nitride under the oxide layer (16) is also shown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.