Method for forming an amorphous silicon programmable element
US5447880A · kind A · utility
14Cited by
9References
14Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Apr 5, 1994 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Apr 5, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an amorphous silicon programable element which requires less than about one square micron of area. The method includes the steps of forming a bottom conductor, depositing an interlayer dielectric above the bottom conductor, forming a via in the interlayer dielectric, depositing an anti-fuse layer above the bottom conductor within the via, and chemical vapor depositing a conductive plug above the anti-fuse layer and within the via. The method may additionally include the step of chemical vapor depositing a top conductor above the conductive plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.