Screening of conductors and contacts on microelectronic devices
US5448179A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 1994 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Jul 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2853
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is disclosed for testing or screening metal or polysilicon conductors and contacts on microelectronic devices that it uses a modified design layout for individual logic gates to enable high current density testing of all such elements used in the final functional circuit. The method uses a special metal pattern adding metal conductor paths to enable high current testing of normal conductors and contacts at an intermediate point during fabrication. The metal layer is patterned a second time to remove the high current paths and enable functional operation. This allows burn-in and screen testing to be performed at higher current densities than would otherwise be possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.