BICMOS cache TAG having small signal exclusive OR for TAG comparison
US5448523A · kind A · utility
5Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1994 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Sep 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache TAG RAM (25) includes a TAG array (26), a small signal exclusive OR logic circuit (33, 34), a sense amplifier (36, 37), and another exclusive OR logic circuit (30, 31). A comparison of a stored TAG address to the input address signal is made by the small signal exclusive OR logic circuit (33, 34) to provide a hit signal very quickly. The stored TAG address that is lost during the exclusive OR operation is recovered by performing another exclusive OR on the match information and the input address signal. By using a small signal exclusive OR circuit to perform a comparison early, the hit signal can be generated very quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.