Decoder and driver for use in a semiconductor memory
US5448527A · kind A · utility
2Cited by
4References
13Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 10, 1993 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Nov 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder formed of multiple circuit blocks each including bipolar transistors Q1 and Q2 having their collectors connected to resistors R1 and R2, respectively, a bipolar transistor Q3 having its collector supplied with a power voltage, and a current source I1 connected commonly to the emitters of Q1-Q3. This circuit configuration permits the decoder and BiCMOS memories using it to operate with a low supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.