Adapters with descriptor queue management capability
US5448702A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1993 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Mar 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor stores descriptors without explicit linkages, in non-contiguous memory locations, and sequentially hands them off to an adaptor which manages scheduling and processing of data transfers defined by the descriptors. Each descriptor is handed off in a request signalling process in which the processor polls the availability of a request register in the adaptor, and writes the address of a respective descriptor to that register when it is available. The adapter then schedules processing of the descriptor whose address is in the request register. The adapter manages a "Channel Descriptor Table" (CDT), which defines the order of processing of descriptors designated by the requests. In effect, the CDT defines a linked list queue into which the adapter installs descriptors, in the sequence of receipt of respective requests. Using the CDT information, the adapter retrieves successively queued descriptors and controls performance of operations (data transfer or other) defined by them. Accordingly, descriptors in the queue are retrieved and respectively defined operations are performed, in the order of receipt of respective requests; as if the descriptors had been stored by the pro…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.