Apparatus and method for booting a multiple processor system having a global/local memory architecture
US5448716A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1992 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Oct 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture and method for booting a multi-processor system having processor local memory and shared global memory, with shared global memory access managed by an atomic memory access controller and cache coherence managed by software. Reset circuits are used to synchronize to a master clock a commonly distributed start signal and processor individualized restart sequences, which reset circuit signals are distributed to reset both local and global memory. Global memory testing is assigned to a processor based upon its rate status in completing an internal test sequence. The systems and methods are particularly suited to booting a group of multiple but relatively independent processors. Furthermore, the practice of the invention facilitates booting of such system when one or more of the processors have been disconnected or failed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.