Transparently inserting wait states into memory accesses when microprocessor in performing in-circuit emulation
US5448717A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1993 |
| Grant date | Sep 5, 1995 |
| Priority date | — |
| Expiry date | Jul 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a register, which when set to a specific value, ensures that memory accesses take at least a specified number of clock cycles. The invention specifically introduces delays into the memory accesses when a memory bank control register is configured to operate the memory bank in a fast-CAS (fast column address strobe) mode of operation. The delays are introduced transparent to the values in the memory bank control register that otherwise controls the operation of the memory bank. The delay introduced by the invention permits an in-circuit-emulation (ICE) system sufficient time to transfer trace data from the microprocessor to the ICE-base.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.