Self-timed digital circuits using linking circuits
US5450020A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1994 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Jun 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Testing digital circuits presents problems because in operation not every "stuck at" fault is detected. The present invention provides linking circuits (12, 13, 14) and functional logic circuits (10, 11) which can be used together to provide a system which ceases operation when a "stuck at" fault occurs. Each linking circuit (12) receives a first input (16) from the output of a previous circuit (10) and a second input (15) from the output of a succeeding circuit (20), both in the vicinity of that linking circuit. The signal coding used is such that in normal operation both these inputs will be different in a predetermined way and if not it is an indication that a fault has occurred. Thus if the inputs do not exhibit the predetermined difference, the linking circuit does not pass its first input to its output. The effect is to stop the system from operating and leave it in a condition from which the location of the fault can be detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.