Data error correcting/detecting system and apparatus compatible with different data bit memory packages
US5450423A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 17, 1992 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Mar 17, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory expansion using memory packages of different generations is performed without unnecessarily increasing the minimum memory capacity of a memory device and while obtaining a high error detecting ability and high reliability. In expanding the capacity of a memory device by using first generation 1M.times.1 bit IC memory packages, second generation 4M.times.4 bits IC memory packages, or third generation 16M.times.8 bits IC memory packages, the total code length is set to 40 bits, a 4's multiple, within a range longer than the total code length necessary for S4ED and shorter than the total code length necessary for S8ED, and a reduced code is used for enhancing the S8ED function. In this manner, wasteful first generation IC memory packages can be reduced in number, and the error detecting ability of a memory device using third generation memory packages can be retained substantially the same as that of a memory device using first generation memory packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.