Flag-based high-speed I/O data transfer
US5450543A · kind A · utility
5Cited by
4References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 11, 1994 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Oct 11, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory address pointer that selects a memory location that is mapped to a video graphics circuit port is incremented only when all bytes in a memory location have been read from or written to by the host CPU. This does not depend on the order in which the host CPU reads or writes data bytes. Therefore a video controller that uses the present invention will work with 8 bit, 16 bit as well as high performance 32 bit input/output instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.