Method and apparatus for cache memory access with separate fetch and store queues
US5450564A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1993 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Feb 3, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-way set associative cache memory system for a parallel-pipelined computer system uses separate queue structures to hold main memory fetch and store requests generated by the central processing unit (CPU). A memory access unit, coupled between the cache memory system and the CPU selects the next request to be processed by the main memory from between the requests at the heads of the fetch and store queues. The request at the head of the fetch queue is preferred over the request at the head of the store queue unless the memory partition to be used by the fetch request is still busy with a previous request while the partition to be used by the store request is idle. Data retrieved from the main memory replaces data in the cache according to an algorithm that prefers empty pages within a set to pages that contain data and prefers pages that do not have pending update requests scheduled to pages that do have pending update requests scheduled. In the event that only pages having pending update requests are found, input requests to the cache are inhibited until at least one fetch request for a page in the set is completed and the page is no longer marked as having a pending update r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.