Circuit and method for selecting a set in a set associative cache
US5450565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1993 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Mar 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A set select circuit and method for selecting a set in a set associative cache in a microprocessor. The set select circuit, responsive to a main clock, includes an input latch coupled to receive select data before the main clock cycle. The input latch is transparent to set select data so that predecoding can begin before the main clock. The input latch latches the set select data on the initial clock edge and holds the set select data during the first half of the main clock cycle. A pre-decoder is coupled to the input latch for receiving and predecoding the set select data, and a decoder is coupled to the predecoder for receiving and decoding the pre-decoded set select data to supply an output to an output latch. The output latch is also coupled to a clock inverter to receive the inverted delayed clock signal. The output latch is transparent during the second half of an inverted delayed clock cycle. The output latch latches the selected set on the initial inverted delayed clock edge and holds the selected set during the first half of the inverted delayed clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.