Compiler with delayed conditional branching
US5450585A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1991 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | May 15, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4451
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimization method or apparatus adapted for use on a compiler for generating machine code optimized for a pipeline processor. A compute-compare-branch sequence in a loop is replaced with a compare-compute-branch sequence. A compute-compare-branch sequence is a sequence of instructions to compute the value of one or more variables, execute a comparison involving the variables, and execute a conditional branch conditioned on the comparison. In the compare-compute-branch sequence, the instructions of the compute-compare-branch sequence are reordered as follows. First, the comparison is executed. In the compare-compute-branch sequence, the comparison involves previously set values of the variables. Second, the computation is executed to compute the current values of the variables. Finally, the conditional branch conditioned on the latter comparison is executed so as to have the effect of executing during the previous execution of the sequence. One or more temporary variables store the previous values of the variables. They are set to the values of the variables at the end of the compare-compute-branch sequence. Before execution of the loop, the temporary variables are set so that t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.