Expanded memory addressing scheme
US5450587A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1992 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Nov 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 31-bit addressing scheme is compatible with current 24-bit addressing schemes and allows an address space of 2 GB to be created. The shared area of the operating system is divided into two separate areas (230, 260), one (230) located at the bottom of the address space and the other (260) at the top of the address space. Between the shared areas (230, 260), a continuous private area (240, 270) is available for use by the applications software. In one embodiment of the invention, the size of the bottom shared area (230) is limited to 1 MB blocks so optimizing the use of private area (230) by applications programs written for 24-bit addressing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.