Gallium arsenide source follower FET logic family with diodes for preventing leakage currents
US5451890A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Apr 11, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0952
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The basic building block of the invention is an inverter gate consisting of two stages: The first stage is an input logic switching stage consisting of a depletion mode pull-up FET whose gate is the input node and whose source-to-drain channel is connected in series through a level-shifting Schottky diode with the source-to-drain channel of an depletion mode pull-down FET between drain and source voltage rails. The source of the pull-up FET is connected to the diode's anode while the drain of the pull-down FET is connected to the diode's cathode and is the output node of the input logic switching stage. The level-shifting diode isolates the output node from the input node, which allows the input voltage to switch rail-to-rail without causing problems. The voltage between the source and drain rails is selected so that the Schottky barrier gate of the enhancement mode pull-up transistor is barely forward biased over the threshold voltage of the Schottky barrier gate junction, so that there is very little current through the gate. The second stage is an inverting stage having an enhancement mode pull-up transistor and a depletion mode pull-down transistor whose source-to-drain channel…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.