Method for reducing errors in switched-capacitor digital-to-analog converter systems and apparatus therefor
US5451950A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1995 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Jan 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched-capacitor DAC system includes two switched-capacitor DACs and a load circuit. The switched-capacitor filter of the first DAC samples a reference voltage source, which produces a reference voltage, at a first rate and the switched-capacitor filter of the second DAC samples the reference voltage source at a second rate, greater than the first rate. The load circuit samples the reference voltage source at a rate such that the level of the reference voltage is the same each time a sample is taken. The load circuit effectively equates the sampling of the two filters and substantially eliminates problems related to gain errors and low frequency quantization noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.