Method for defining and using a timing model for an electronic circuit
US5452225A · kind A · utility
31Cited by
9References
39Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 24, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Jan 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method that first simulates the electronic circuit of each cell type within a circuit cell library using combinations of input transition time and load capacitances. The method reduces the results of the simulation to one of several models for the cell type. The method then reads an actual circuit description of the electronic circuit, and applies the models to the actual cells used in the circuit to determine signal delay through the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.