Fully static CAM cells with low write power and methods of matching and writing to the same
US5452243A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Jul 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are disclosed for writing to a large content addressable memory (CAM) array without causing substantial power supply current surges, for providing fully static CMOS memory cells, for providing a consistent precharge of bit and bit bar lines, for providing a column write capability, and for increasing a read current while reducing a read disturbance probability. Each memory cell in the CAM array has (a) a data write circuit for accepting data, (b) a latch circuit for latching the data in the memory cell, (c) a hold circuit to allow holding the data or writing new data, (d) a data compare circuit for comparing the new data to the stored data, and (e) a data read circuit for reading the stored data. A memory cell further has control lines including (a) a read row enable (rren) line for enabling and disabling the data read circuit, (b) a match line for indicating a match between the stored data and the new data, (c) a write row enable (wren) line for enabling and disabling a row for a write operation, (d) a write column enable (wcen) line for enabling and disabling a column for a write operation, (e) a bit line, (f) a write column enable bar (wrenb) line for enab…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.