Data multiplexing system having at least one low-speed interface circuit connected to a bus
US5452307A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Oct 20, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/1611
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A data multiplexing system comprising a plurality of data multiplexing buses through which a plurality of low-speed digital signals are collected into, and distributed from, a multiplexer/demultiplexer. In a data multiplexing mode, the low-speed digital signals entered from a plurality of low-speed transmission lines have their signal format converted by respectively corresponding low-speed interface circuits, and the resulting signals are multiplexed in time slots designated within a multiplexed signal of primary level on the up bus line of the corresponding data multiplexing bus, under the controls of respectively corresponding bus control circuits. The high-speed multiplexer collects the primary multiplexed signals on the up bus lines of the plurality of data multiplexing buses, and further multiplexes the collected signals up to a predetermined signal level. Thereafter, it sends the resulting secondary multiplexed signal to a high-speed interface module having a high-speed transmission line interface. The high-speed interface module converts the received secondary multiplexed signal so as to match the interface of a high-speed transmission line, and sends the resulting signal t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.