Error correction code on add-on cards for writing portions of data words
US5452429A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1993 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Nov 17, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.