Processor and cache controller interface lock jumper
US5452463A · kind A · utility
4Cited by
17References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1993 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Sep 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system including at least one processor and a cache subsystem, in which computer system locked cycles are generated, include a jumper assembly for operatively connecting the at least one processor and the cache subsystem so as to render locked cycles cacheable if the computer system includes only one processor and non-cacheable if the computer system includes more than one processor. A method according to the present invention includes the steps of determining whether there is one or more than one processor in a computer system, and then rendering locked cycles cacheable or non-cacheable accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.