Five transistor memory cell with shared power line
US5453950A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1995 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Jan 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Static random access memory cells (SRAMS) containing five MOS transistors are configured in a memory array such that only three bitlines are required for two cells. A first bitline is coupled to a first side of a first memory cell, and a second bitline is coupled to a first side of the second memory cell. The first and second memory cells share either a common power bitline or a common ground bitline. A control circuit executes a special write operation to write a low logic level on the second side of the memory cells. The control circuit is coupled to the first, second, and third bitlines to generate a first differential voltage across the memory cells that is lower than the operating voltage on the third bitline and to generate a second voltage lower than the operating voltage on the second bitline when storing a low logic level on the second side of the first storage cell. To perform a special write operation on the second storage cell, the control circuit generates the first differential voltage on the third bitline and the second voltage on the first bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.