Semiconductor memory device having a self-refreshing control circuit
US5453959A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 30, 1994 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Mar 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device capable of a self-refreshing operation with a refresh-initiation signal generated in the memory device has a self-refreshing control circuit. A self-refreshing operation is automatically effected, without externally supplied clock signals, with a specific refreshing cycle having an internally set mode entry time period, a burst refresh time period and an internally set pause time period. These time periods are detected by a single counter circuit arranged to count pulses produced from a basic clock pulse signal generated by an oscillator. The burst refreshing is effected with the pulses contained in a pulse signal generated in synchronization with the basic clock pulse signal from the oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.