Address verification system using parity for transmitting and receiving circuits
US5453999A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1994 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Apr 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address verification system for providing address error detection whether the error originates at the address generation circuitry, the address transmission path, or the address receiving circuitry. Multiple address generation circuits which simultaneously generate equivalent addresses each have associated parity generation circuits to provide parity bits for its associated address. Monitoring for unequal parity bits generated by the multiple parity generation circuits allows detection of address generation errors. Predetermined address parity bits for each potential address to be sent to the address-receiving circuitry are stored at the address-receiving circuitry to be compared to the parity bits issued by the multiple parity generation circuits. The predetermined address parity bits are determined prior to real-time address transmissions of the system, so that manual or automatic verification of the predetermined parity bits can be performed to ensure correctness of the predetermined address parity bits. The use of predetermined address parity bits which are stored at the address-receiving circuitry allows detection of address transmission and address receipt errors. Monitori…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.