Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units
US5454090A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1994 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Apr 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for furnishing instructions having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, includes a memory; an address register having contents pointing to an instruction to be processed in said memory; an instruction register for receiving a loading of the instruction during an instruction loading phase; an arithmetic calculation unit for calculating addresses; an incrementing stage for incrementing the contents of said address register; and a multiplexer for selecting a calculated address or an incremented successor address. One embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit. Another embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.