Method and apparatus for detecting multiple matches in a content addressable memory
US5454094A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 1993 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Jun 24, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90339
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for detecting multiple matches or hits in a content addressable memory (CAM) are disclosed. The circuit includes a logarithmic index generator or encoder, and a converter which provides a unary signal to an attached random access memory (RAM) in order to protect the RAM from simultaneous multiple addressing attempts. The circuit also includes a plurality of inverters for inverting the unary signal, and generates a signal indicating the presence of multiple matches in the content addressable memory when corresponding digits of the inverted unary signal and an address signal are both asserted. The circuitry for generating the multiple match signal includes a plurality of AND gates coupled to output lines of the CAM, a plurality of line transistors, and a pull-up transistor coupled to a multiple match or hit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.