Cache memory support in an integrated memory system
US5454107A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1993 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Nov 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/125
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.