Process for forming solid conductive vias in substrates
US5454928A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1994 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Jan 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/128
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of forming solid metal vias extending between the top and bottom surfaces of a substrate with the ends of the vias being substantially coplanar with the top and bottom surfaces. The method includes the steps of forming holes through the substrate, plating the interior of the holes with excess metal to fill the holes and extend beyond the ends of the holes, heating the substrate to cause the metal to melt and consolidate to form solid vias with domed ends, and lapping the top and bottom surfaces of the substrate to remove the domes. Conductive layers may then be formed over the vias. These layers may have windows over a portion of each via to provide an escape route for expanding fluids during further processing of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.