Method of fabricating an ASIC cell having multiple contacts

US5455191A · kind A · utility

Assignee

• Synergy Semiconductor Corporation · US

Inventors

• David A. Gray · Saint Paul, US
• Thomas S. Wong · San Jose, US

Key dates

• Filing date: Aug 31, 1992
• Grant date: Oct 3, 1995
• Expiry date: Aug 31, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/901

Abstract

A high density ASIC cell provides customization solely at the polysilicon #2, insulator #3 levels. High density is achieved by permitting a metal #1 trace to traverse an underlying transistor, without requiring space between adjacent transistors to facilitate traversing interconnects. Oversized collector and emitter traces at the polysilicon #1 level make downward contact with the collector and base regions of the underlying transistor, and provide redundant upward contact with collector and emitter polysilicon #2 traces. Contact between the transistor base and a base polysilicon #2 trace is also made. The polysilicon #2 emitter, base and collector traces provide a replicated, unvarying pattern that preferably defines a 3.times.3 matrix of potential contact points for overlying metal #1 traces to contact the underlying transistor's emitter, base and collector. A metal #1 trace can traverse this 3.times.3 matrix simply by not providing openings in the insulating #3 layer beneath the traverse. If a metal #1 trace is to contact a region of the underlying transistor, an opening is made in the insulation #3 layer over the necessary contact in the 3.times.3 matrix at the polysilicon #2 l…