Duty cycle control circuit and associated method
US5455530A · kind A · utility
8Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1994 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Mar 9, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle control circuit, and an associated method, generates an output clock signal having a duty cycle which differs by a desired amount with the duty cycle of an input clock signal. Offset bias signal circuitry generates an offset bias signal which offsets a copy clock signal and an inverted copy clock signal relative to one another by a selected offset bias. The duty cycle of the output clock signal differs with the duty cycle of the input clock signal by an amount which is related to the amplitude of the offset bias signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.