Computer design system for mapping a logical hierarchy into a physical hierarchy
US5455775A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1993 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Jan 25, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer design system is used to map a logical hierarchy corresponding to the logical functions of an electronic system into a physical hierarchy corresponding to the physical positioning of the actual electronic components which will implement the logical functions of the system. The logical hierarchy contains several levels of logical entities connected by signals, and the physical hierarchy contains physical packages corresponding to electronic components, such as integrated circuits. The mapping is accomplished by designating partition group assertions (PGAs) for each of the logical entities in the logical hierarchy. Each PGA corresponds to one of the physical packages in the physical hierarchy. Each entity is grouped by common PGA designation, and each signal of each entity is classified as external, if the signal connects entities located on different physical packages, or internal, if the signal connects entities located on the same physical package. The physical hierarchy for the electronic system is generated using lists of these logical entity groupings and signal classifications. An advantage of the present invention is that partitioning of a logical design into a phy…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.