Fault tolerant address translation method and system
US5455834A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1993 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Jun 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed wherein error detection codes are used for detecting and handling hardware errors in a memory table. Before each address and associated data are entered into the memory table, an error detection code is generated for both the address and the data. The address, data, and corresponding error codes are stored in the same entry line in the memory table. When the table receives an input address from a CPU, the input address is compared to all of the addresses stored within the memory table. If any stored address matches the input address, the matched address is outputted along with its associated data and its corresponding error codes. The matched address and its associated data are each processed with its corresponding error code to determine whether the outputted address and data are identical to the address and data used to generate the error codes. If either the address or the data has been altered by a hardware error in the memory, an error signal is generated to indicate that the outputted information is invalid. This error signal causes the outputted information to be ignored. The hardware error is thus detected and tolerated. The memory table al…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.