Memory system for loading peripherals on power up
US5455923A · kind A · utility
Inventor
Key dates
| Filing date | Jan 14, 1993 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Jan 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory connected to state logic is provided for autoloading peripheral target devices at power-on or system reset. The memory is preloaded with commands and data. At power-on or system reset the commands are executed in sequence, transferring data to selected target devices. Data is output in bit-serial fashion on a single line. Target devices are individually selected through use of separate clock lines. Clock signals on the clock lines can be internally generated using the state logic or a target-device-supplied clock can be received under program selection. The system reset signal is intercepted and retransmitted to control target device mode. System reset polarity, enable signal polarity, data block length, clock direction, internal clock frequency, and power-saving shutdown upon completion of all transfers are all programmably selectable features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.