Logic simulator employing hierarchical checkpointing
US5455929A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1993 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Oct 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3457
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simulator system of a digital network which may contain a memory. The system includes at least three hierarchical data storage buffers 18, 20, 24, 26 for storing the simulated network signals for simulated registers and combinatorial logic at the close of each simulation cycle. Each buffer 20, 24, 26 has a plurality of entries comprising a periodic sampling, sometimes referred to as checkpointing, of the next lower storage buffer. The system also includes a change management list 30 and a memory data array 32 for respectively storing time/address pairs and time/value pairs to identify the time, address and value of memory writes. These pairs of data are updated (i.e., checkpointed) each time a selected data storage buffer 24, 26 starts to have previously written locations overwritten by newer data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.